When NMOS, PMOS and CMOS technologies were first put into production in the semiconductor industry most metal oxide semiconductor field effect transistors (MOSFETs) were fabricated with relatively thick gate oxides. For most applications gate oxides or gate dielectrics are used to isolate a conductive gate region from a substrate region which is usually called a channel. The thicker gate oxides gave the advantages of: (1) almost no leakage current resulting from valence band to conduction band transitions; (2) less MOSFET degradation with time, i.e. improved lifetime by reducing a well-known gate damaging hot electron injection phenomena; and (3) less Miller Capacitance, i.e. less gate-to-source and gate-to-drain capacitance which helps to improve on-to-off and off-to-on switching speed. However, the thicker gate oxides resulted in low gain or low current capability and short channel effects such as Drain Induced Barrier Lowering (DIBL) which adversely affect MOSFET turn on voltages or threshold voltages. DIBL is a phenomena that drastically reduces threshold voltages as the channel region length is reduced or, in other words, as the channel becomes a short channel.
To improve the performance and density of the MOSFET, the semiconductor industry began to shrink the geometry of this device not only in terms of surface area but also in terms of dielectric thickness which primarily involved the gate dielectric. As the gate dielectric was reduced in thickness, MOSFETs gained the advantage of higher source-to-drain currents which improved gain and resulted in a reduction of unwanted short channel behavior. The thinner gate dielectric also produced undesirable results, such as: (1) a higher gate current leakage from source-to-gate, from drain-to-gate and from channel-to-gate due to hot carrier effects; (2) valence band to conduction band current leakage in the source and drain; (3) strong degradation of the gate and therefore a shorter lifetime; and (4) larger Miller Capacitance which slowed the device. As the MOSFET size continued to shrink towards submicron sizes, it was realized that a new technology would have to be developed to keep current leakage and capacitance from becoming too extreme and performance limiting. This new technology had to be capable of further size reduction due to the fact that all the MOSFETs used up to this point in time were no longer electrically or mechanically capable of further reduction.
To correct some of the problems resulting from thin gate oxides and to allow further device size reduction in MOSFETs, Lightly Doped Drain (LDD) transistor structures were researched. LDD transistors helped reduce hot carrier effects and improve MOSFET lifetime as is taught in U.S. Pat. No. 4,951,100, issued Aug. 21, 1990, by Louis C. Parillo, entitled, "Hot Electron Collector for a LDD Transistor" and assigned to the assignee hereof. Although LDD transistor structures improved lifetime by reducing hot carrier effects, the structures, in general, did little to improve upon Miller Capacitance switching speed problems, short channel effects, and other typical thin dielectric MOSFET shortcomings. Not being able to shrink the presently existing LDD structures below critical dimensions of roughly 0.5 micron (.mu.) without introducing heavy current leakage and DIBL also hindered further progress.
A transistor structure referred to as an "Inverse T LDD" structure was also proposed. Although this transistor structure and other variations of this type of structure made some improvements over most thin gate MOSFET structures and LDD transistor structures, a noted disadvantage of Inverse T LDD MOSFETs is large pitch and therefore poor circuit density. In addition, the Inverse T LDD transistor structure still does not greatly improve upon valence band to conduction band transition leakage current or Miller Capacitance.